Pulse doppler radar receiver with a circuit for reducing spurious signals

ABSTRACT

A pulse Doppler radar receiver which continuously monitors successively obtained amplitude values Ao through An with the disrupted amplitude values which deviate by a prescribed value from an interpolation value obtained from adjacent undisturbed amplitude values are determined and are limited to a value obtained from the interpolation value or from the largest or smallest adjacent undisrupted amplitude values and are substituted for the disrupted values. The apparatus includes an interpolation circuit which includes the shift register and limiter with the memory for adjusting the output signal level of the limiter.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates in general to pulse Doppler radar receiversincluding means for a large plurality of range channels and movingtarget filters and rectifier arrangements for obtaining the videosignals and in which the video signals are supplied to an evaluationmeans through a postdetection-integration circuit and a video thresholdcircuit.

2. Description of the Prior Art

A circuit arrangement for the suppression of interfering signals for apulse radar receiver which are supplied and an equivalent signal so asto suppress spurious signals is disclosed in British Pat. No. 1,407,467entitled "Improvements In Or Relating To Interference SuppressionCircuits For Radar Receivers". The circuit arrangement described in thispatent utilizes a delay network which is particularly designed forslowly swept or frequency modulated spurious signals which have a longduration relative to the useful signals.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a radar receiverwhich is capable of restoring the signal progression disrupted due tothe absence of individual signal amplitudes or due to single shot pulseswamping to obtain the original form so that the detection probabilityof generally weak moving target echo signals can be detected. Thecircuit can be designed and constructed within appropriate limits. Theinvention provides a circuit arrangement for limiting and substitutingindividual, disrupted signal amplitudes which is inserted between therectifier and the postdetection-integration circuit in conjunction withan interpolation circuit which comprises a shift register and a limiterbetween the input and output and has two circuit branches connected inparallel and wherein the interpolation circuit and a memory in thesecond circuit branch adjusts the limiting of values of the limiter.

The successively obtained amplitude values are continually observed andcompared to the directly adjacent amplitude values or by means ofcomparison to an interpolation value from said amplitude values so thatthe amplitude value deviations of a prescribed value from the maximum orminimum values or from the interpolation value are determined and thedisrupted amplitude values are limited to an amplitude value obtainedfrom the maximum or minimum values or respectively substituted by avalue obtained from the interpolation value and are substituted into theoutput signal.

Signal values which are disrupted due to asynchronous pulses are limitedto an amplitude value matched to the remaining signal progression bymeans of a limiter circuit with a locked threshold which is controlledby the existing interpolation value or by the maximum or minimum values.Lost or blanked out signal values are replaced by means of asubstitution circuit wherein the equivalent value is derived from themaximum or minimum value or respectively from the interpolation value.With the existence of a symmetrical antenna function, the interpolationoccurs by means of mean value formation from two supporting values whichare taken from the signal progression before and after the signal to bechecked.

Other objects, features and advantages of the invention will be readilyapparent from the following description of certain preferred embodimentsthereof taken in conjunction with the accompanying drawings althoughvariations and modifications may be effected without departing from thespirit and scope of the novel concepts of the disclosure and in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 comprises a plot of the amplitude of received signals versustime;

FIG. 2 comprises a plot of amplitude versus time of the limited valuesallocated to the received signals;

FIG. 3 is an amplitude versus time plot after correction has beenapplied;

FIG. 4 is a simplified block diagram of the invention;

FIG. 5 is a block diagram of the interpolation circuit of the invention;

FIG. 6 illustrates a modification of the interpolation circuit of theinvention;

FIG. 7 illustrates a further modification of the interpolation circuitof the invention;

FIG. 8 comprises a vector diagram illustrating the signal relationshipsfor the circuit of FIG. 7; and

FIG. 9 is a block diagram of the interpolation circuit which has twothresholds.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

As illustrated in FIG. 1, the amplitude A of a function of time for asequence of discrete amplitude values A0, A1 . . . An which correspondto the individual samples from the echo signal of a target afterrectification at times T0, T1 . . . Tn is plotted. Such data can besamples of a pulse radar which occurs at the clock rate of the pulseradar repetition frequency for a respective distance range. Except forthe unusually high amplitude value A3 which can be attributed to anasynchronous noise pulse, the envelope of the illustrated amplitudevalues varies as a function of time as a bell-shaped distribution. Suchenvelopes occur in a radar device due to the fact that the radiationpattern of the antenna is swept over a target which is either fixed ormoving in the radial direction or where a target moving tangentiallycrosses through the fixed radiation pattern. Such an envelope can bedetermined for each radar receiver from the characteristics of theantenna and from the size of the targets which are to be detected by theantenna. The amplitude of a signal at time T3 which was either disruptedby a noise pulse or dropped out for some other reason can bereconstructed from the envelope.

FIG. 2 is a plot of the limiting values Bo . . . Bn corresponding to thesampling times of the received signals which are illustrated in FIG. 1and which are obtained by means of interpolation of measured supportingvalues for the case of a single-shot disruption and which represent thethreshold value of a circuit for limiting the noise pulses at the sametime.

FIG. 4 illustrates a simplified block diagram of a pulsed radar with aninterpolation circuit which has an antenna 1 which supplies an outputthrough a transmit/receive switch 2 which is connected to a transmitter3 and a clock generator 2a. The changeover of the transmit/receiveswitch 2 is controlled by the clock generator 2a. A mixer 4 receives theoutput of the antenna 1 and an input from a heterodyne oscillator 5. Theecho signals of the individual targets are separately processed bysuitable circuits whereby range channels for example can be employed. Asingle such branch is illustrated for a specific range in FIG. 5. Theecho signals of only one target lying in a specific range pass into aspecific range channel without mixing with echo signals of other targetsoccurring. Echo signals of asynchronous pulse jammers according tostatistical distribution thus will fall in most distance ranges withonly one pulse. With digital processing the output of the mixer stage 4is passed to an analog/digital converter 6 which supplies an output to adigital working permanent echo filter 7 which in turn supplies an outputto a rectifier or detector circuit 8 which adds in case of quadraturechannels the amplitudes of the signals. The rectified signal of therectifier 8 is supplied to an interpolation circuit 9 which supplies anoutput to a memory and low-pass filter circuit(postdetection-integration) 10. A threshold circuit 11 receives theoutput of the memory and low-pass filter circuit 10 and supplies anoutput to a visual display means 12.

FIG. 5 illustrates in detail a simple interpolation circuit 9 which alsoincludes a threshold limiter circuit which removes the asynchronousdisruptive pulses. Such pulses can be produced for example by theignition systems of motor vehicles or by external radar systems and aresuppressed without noticeably influencing the signal passage at theoutput of the memory and low-pass filter circuit 10 which comprises anintegrator. Because of the knowledge of the signal progression at aspecific location of the radar receiver, conclusions can be drawn frommeasured supporting values concerning the signal progression in theenvironment. So as to eliminate noise signals the environment ismeasured and the chronological progression of the undisturbed signal isinterpolated therefrom. In principle, all known interpolation methodscan be applied. A preferred embodiment uses the mean value formationfrom two adjacent amplitude values. A maximum or, respectively, minimumvalue formation is also possible. Depending upon the type of theinterpolation method utilized, a different number of supporting valuesis necessary. Since target signals are generally subject to asymmetrical antenna function as illustrated in FIG. 1, it isadvantageous to measure the supporting values before and after a noisesignal.

The interpolation and limiter arrangement illustrated in FIG. 5 utilizesmean value formation or linear interpolation between two signalamplitudes whereby the noise signal occurs in only one reception period(N=1). The supporting values are obtained during one respectivereception period before and one period after the reception period whichis to be currently checked. The signal of the observed reception periodis limited to the interpolated value in this circuit and it serves asthe supporting value during the next reception period. When, forexample, the received signals A2, A3 are observed in succession at timesT2 and T3, then the first interpolation value is obtained from theamplitude values A1 and A3 by using mean value formation. Since a highnoise pulse occurs at time T3, the limiter value of B2 illustrated inFIG. 2 also has a high value which extends above the normal bell-shapedprogression. Since the limiter value B2 is greater than the amplitudevalue A2, no operation will be performed on the signal progression. Thenext interpolation value for inspecting the signal amplitude at time T3is formed from the amplitude values A2 and A4. The limiter value B3obtained therefrom limits the high noise signal adjacent time T3 to anormal signal amplitude of A'3 which corresponds to B3 as illustrated inFIG. 3. During the next reception period, the corrected signal A'3 isutilized as a supporting value for the next interpolation together withthe signal amplitude A5. Thus, when an unusually high signal is receivedwhich falls out of the normal pattern of the bell-shaped curve thesignals on opposite sides of such unusual signal are utilized to form amean value for interpolation and such value is utilized.

Signals appearing at the input E of the interpolation and limitingcircuit 9 in FIG. 5 are supplied to a shift register SR which is shiftedat the clock frequency of the radar repetition frequency rate. Thenumber of N memory locations in the shift register depends on the numberof possible noise pulses which can successively occur in the input E.The signal amplitudes at the output of the shift register SR are limitedin amplitude by a limiter BS. The threshold value B of the limiter BSrepresents a locked on threshold which is constantly resupplied to thelimiter BS from an interpolation stage IS. The signals from the input Eof the circuit and the memory SP which is connected to the limiter stageBS are supplied to the interpolation stage IS which is designed as astage for forming a mean value. When the output signals of the shift SRare greater than the interpolated value by a prescribed amount suchvalue is replaced or, respectively, limited by the interpolated value inthe embodiment illustrated in FIG. 5. The limited signal A' forms on theone hand the output of the circuit and on the other hand is read intothe memory SP at the clock frequency of the radar repetition frequencyand is delayed therein by a radar reception period. The describedcircuit is very effective when the number of successive occurring noisepulses are small and also when the number of memory locations in theshift register SR is small. Thus, the circuit is particularly suited foremployment directly behind the analog to digital converter 6 (N=1), orbehind a simplex canceller (N=2), or behind a duplex canceller where(N=3).

When the circuit is utilized in front of the rectifier circuit 8, than atwo-sided limiter having thresholds of +B and -B must be utilized. Thisis illustrated in FIG. 6 and furthermore a pair of rectifiers GL must beconnected in the inputs of the interpolation stage IS as illustrated inFIG. 6.

In each instance, the interpolation stage can also be designed so thatthe limiter value B is obtained from the larger amplitude of the signalE or the output signal of the memory SP (maximum value formation).

When the circuit is employed in a complex functioning system with Ichannel and Q channel (inphase signal and quadrature signal), then itcan be useful to also calculate a complex limiter value B_(I) and B_(Q)and such arrangements are illustrated in FIGS. 7 and 8.

When the input signals A₀ through A_(n) are divided into real andimaginary components A_(n) =A_(In) +jA_(Qn), then the limiter values canbe calculated for example as illustrated below although any otheralgorithm could be utilized. ##EQU1##

In the sample embodiments described so far, it has been chiefly thelarger noise pulses which were detected and replaced by interpolation.

It is also possible to replace signals which are too small that is,which are smaller than the adjacent supporting values by a prescribedamount. This allows gaps in the signal progression to be corrected.

In FIG. 7 a pair of shift registers SR respectively receive the inputsA_(In) and A_(Qn) which signals are also supplied to the interpolationstage IS. The output of the shift registers SR and SR are respectivelysupplied to the interpolation stage IS as well as to limiter circuits BSwhich are in the respective channels. Memories SP and SP receive theoutputs of the two limiters BS respectively and supply inputs to theinterpolation stage IS, and the two outputs are supplied from thelimiter circuits BS and BS.

FIG. 8 comprises a phase diagram illustrating the relative phase of thesignals in the circuit of FIG. 7.

It is also possible to replace signals which are too small that issmaller than the adjacent supporting values by a prescribed value so asto correct gaps in the signal progression.

FIG. 9 is an illustration of a circuit for detecting and correcting forsignals which are too large as well as too small. For the purpose ofsimplification, a circuit is illustrated which can be utilized behind arectifier or respectively, a amplitude adder (compare FIG. 6).

The amplitude values A_(n) appearing at the input E of the circuit aredelayed by a shift register SR by N time intervals T where N correspondsto the number of successively appearing noise pulses at the input E. Thesignal A_(n-N) is delayed and supplied to the limiter circuit BS. Whenthe signal A_(n-N) is greater than the upper limiter thresholdB_(o)(n-N), or smaller than a lower limiter threshold value B_(u)(n-N),it is replaced by the interpolation value 1/2(A_(n) +A_(n-N-1) ') andwhen not, smaller or greater than the limiter thresholds it is suppliedat the output and also to the memory SP unlimited as the signal A_(n-N)'. The output signal of the memory SP (A_(n-N-1) ') and the input signal(A_(n)) are supplied to the interpolation stage IS. On one hand, theinterpolation value as, for example 1/2(A_(n) +A_(n-N-1) ') is formed inthe interpolation stage IS and, on the other hand, the upper limit value(B_(o)(n-N) =x·1/2(A_(n) +A_(n-N-1) ') and the lower limiter value(B_(u)(n-N) =y·1/2 (A_(n) +A_(n-N-1) ') are calculated. The factors xand y indicate the tolerances for the response limits and for examplex=1.5 and y=0.5.

In the above example, each value A_(n-N) to be investigated is replacedby the mean value of its adjacent supporting values A_(n) and A_(n-N-1)' when it is greater than this mean value by a factor of 1.5 or when itis smaller than the mean value by a factor of 0.5. The value A_(n-N) 'investigated in such manner and if required corrected then again servesduring the next reception period after a time interval T for the meanvalue formation from the values A_(n+1) and A_(n-N) ' for investigatingthe value of A_(n-N+1).

It is seen that this invention allows correction by use of interpolationof radar signals which fall above or below the known expected amplitudevalues.

Although the invention has been described with respect to preferredembodiments, it is not to be so limited as changes and modifications canbe made which are within the full intended scope of the invention asdefined by the appended claims.

I claim as my invention:
 1. A pulse Doppler radar receiver for receivingradar video signals with apparatus for a large number of range channelsand moving target filters and comprising, rectifier arrangements fordetecting the radar video signals and in which said radar video signalsare supplied to an evaluation means through a postdetection-integrationcircuit (10) and a video threshold circuit (11) including aninterpolation circuit (9) for limiting and substituting individual,generated corrected amplitude signals for disrupted signals which are inerror due to their amplitude variations and which includes aninterpolation stage (IS), said interpolation stage being connectedbetween said rectifier (8) and said postdetection-integration circuit(10), and said interpolation circuit (9) including a shift register (SR)and a limiter (BS) between its input and its output in a first of twocircuit branches which are connected in parallel and including aninterpolation stage (IS) and a memory (SP) in a second of said twocircuit branches; and said limiter (BS) is controlled with an outputfrom said interpolation stage (IS) which varies as a function of theinputs to said interpolation circuit so as to prevent extreme variationsof vided signals.
 2. A pulse Doppler radar receiver according to claim1, characterized in that the largest amplitude value determined bycomparing the amplitude of signals adjacent to the disrupted signal isemployed as the generated corrected amplitude signal.
 3. A pulse Dopplerradar receiver according to claim 1, characterized in that the smallestamplitude value determined by comparing the amplitude of signalsadjacent to the disrupted signal is employed as the generated correctedamplitude signal.
 4. A pulse Doppler radar receiver according to claim 1characterized in that said interpolation circuit (9) is mounted in thesignal path after an analog-to-digital converter (6) for digital signalprocessing.
 5. A pulse Doppler radar receiver according to claim 1characterized in that said interpolation circuit (9) is mounted in thesignal path after a permanent echo filter (7) which may be a simplexcanceller, or duplex canceller.
 6. A pulse Doppler radar receiveraccording to claim 1 characterized in that said interpolation circuit(9) is mounted in the in-phase signal channel and quadrature signalchannel of a system with a quadrature rectifier.
 7. A pulse Dopplerradar having an output terminal with a moveable antenna, detecting meansfor detecting a bell-shaped series of pulses from a target, means fordetecting when one of said pulses falls outside a normally expectedamplitude range, means for producing a substitute pulse for said pulsewhich falls outside the expected range and said means for producing asubstitute pulse furnishing said pulse which falls outside said expectedrange to said output terminal and wherein said means for producing asubstitute pulse produces by interpolation said substitute pulse with anamplitude that is between the amplitudes of pulses immediately beforeand immediately after said pulse which falls outside the expected range.